1. Field of the Invention
The present invention relates generally to television systems, and more specifically to a method and apparatus for generating a clock signal synchronized with time reference signals (e.g, HSYNC) associated with a television signal.
2. Related Art
Phase-lock-loop circuits (PLLs) are often used to generate a clock signal synchronized with an external time reference signal. FIG. 1 is a block diagram of illustrating an example implementation of a PLL circuit. PLL circuit 100 includes phase detector 110, charge pump 120, filter 130, voltage controlled oscillator (VCO) 140, and frequency divider 150. Phase detector 110 compares an external time reference signal received on line 101 and a signal having a fraction (determined by frequency divider 150) of the frequency of the generated clock signal received on line 151. The two signals are referred to as f1 and f2 for brevity.
Phase detector 110 provides on line 112 a voltage signal indicative of the difference of the phases of f1 and f2. The signal on line 112 charges charge pump 120. When frequencies f1 and f2 are synchronized perfectly, the signal on line 112 may be at zero voltage and charge pump 120 may not be charged. Filter 130 is generally designed as a low pass filter to eliminate undesirable high frequency components. When the frequencies f1 and f2 are close, but not equal, line 123 will carry a voltage signal proportional to the difference in frequencies.
VCO 140 is designed to generate a clock signal with a predetermined frequency (equal to the desired clock frequency). The predetermined frequency equals f2.times.N, where N is the divisor in the frequency divider 150. When f2 is not an integral multiple of f1, a multiplier can be used to multiply frequency f1 and the value of n is chosen to achieve the desired frequency f2. The frequency of VCO 140 is altered depending on the voltage level received on line 123. The voltage level on line 123 is generated so as to achieve a synchronization of the frequencies f1 and f2. The voltage level on line 123 may be amplified if needed to achieve such a synchronization.
Frequency divider 150 divides the frequency of clock signal received on line 145 by a factor of N. In a steady synchronized state, f1=f2 and the clock frequency generated by VCO 140 equals N.times.f1. Thus, by a proper choice of N, a clock signal of a desired frequency can be generated.
PLL circuits such as the one described in FIG. 1 are generally acceptable when the value of N is small (e.g., about 10). However, as the value of N becomes large, synchronizing the clock signal with the external time reference signal can become problematic as the correction of any misalignments between f1 and the generated clock signal occurs only once every cycle of the reference clock f1.
The large correction times can be problematic in several environments such as display units which operate at high speeds. The absence of synchronization can result in display artifacts as is also well known in the art. For example, a television system may be used for displaying images encoded in television signals as well as images representative of services/data accessed on a network. One or more embodiments of such television systems are described in Related Patent 1 noted above.
In such systems, the display of network application data may need to be synchronized with the time reference signals associated with a television signal. To process and display network application data, clock signals having a frequency of as high as 40 MHZ may be required. The time reference signals of television signals can have a frequency of as low as 30 KHz. Thus, magnifications of the order of few hundreds to a thousand (N=100 to 1000) may be required. In such situations, PLL circuits such as the one described with reference to FIG. 1 may not be acceptable.
Therefore, what is needed is a PLL circuit for generating a clock signal, which is synchronized well even in situations when the clock signal has a frequency substantially greater than the frequency of the external time reference signal. In addition, the PLL should operate in situations such as the television systems (e.g, those described in Related Patent 1) which provide combined display of television signal images and network application data image.